Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one M.times.N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1b. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. A plurality of memory cells 14 connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art FIG. 1b. Each stacked gate 14c is coupled to a word line (WL0, WL1, . . ., WLn) while each drain of the drain select transistors are coupled to a bit line (BL0, BL1, . . ., BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell 14 can be addressed for programming, reading or erasing functions.
Prior art FIG. 1c represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1a and 1b. Such a cell 14 typically includes the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art FIG. 1b). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c.
The process for making such NAND type flash memory devices includes numerous individual processing steps. There are numerous concerns associated with making flash memory devices that provide consistent performance and reliability. For example, the thicker the floating gate, the more likely undesirable cracking occurs in the tungsten silicide layer and the more likely etch problems occur due to high aspect ratios and high topographies. However, the thicker the floating gate, higher the stress released on the tunnel oxide layer, improved tunnel oxide reliability, improved conductivity and better circuit performance result. The thinner the floating gate, the more likely undesirable punch through during etch occurs, especially the Poly 1 contact etch for the select gate, as well as an undesirable increase in pinhole defects. Further, when the thickness of the Poly 1 is too thin, an HF dip cleaning step (prior to forming the ONO multilayer dielectric film) may degrade the Poly 1 and attack the tunnel oxide.
If the doping level is too low in the floating gate, wordline resistance and contact resistance become undesirably high, and specifically resistivity for the select gate becomes undesirably high. However, low doping results in a smooth tunnel oxide--floating gate interface. Low doping also results in fewer charge gain (loss) problems. If the doping level is too high in the floating gate, undesirable dopant segregation to the tunnel oxide occurs, undermining the tunnel oxide integrity. Undesirably high doping levels lead to severe surface roughness between the floating gate and the tunnel oxide, resulting in high local electric fields, lower oxide dielectric strength, and program/erase endurance cycling problems.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality and more efficient methods of making such memory cells.